The fix does exactly that (I know this for sure, because I have developed it and I have two working 24LCxx EEPROMs right in front of me ;- ). In order to generate the above sequence, call CreateReadTransaction(..., address, 2) from Chris' example. The address will be written onto the bus as ADDR-HI and ADDR-LO.
Could you please share the logic analyzer output? (Please note that Start condition is just High -> Low transition on SDA while SCL is High, it is not a bit with duration of the clock signal period).
Yeah, sorry CW2 - I misunderstood the internalAddress param on CreateReadTransaction (I thought it was the device address) so the extra Start wasn't getting generated. I fixed up the code and now it works perfectly - the logic analyzer output looks exactly like the datasheet.
Many thanks for your help - I still have a lot to learn but getting great help like this is always appreciated!