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Mike P

Member Since 15 Jul 2011
Offline Last Active Jul 08 2012 09:27 AM
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#18044 Compiling firmware

Posted by Mike P on 15 September 2011 - 12:55 PM

There are several really good posts buried in the forum on how to compile the Netduino firmware from source code.
I've managed to get as far as this error:

C:\GCC\bin\arm-none-eabi-ld.exe: C:\MicroFrameworkPK_v4_1\BuildOutput\THUMB\GCC4.2\le\FLASH\release\Netduino\bin\tinyclr.axf section ER_FLASH will not fit in region LR_FLASH
 C:\GCC\bin\arm-none-eabi-ld.exe: region LR_FLASH overflowed by 65128 bytes

Now I have read this very helpful post by CW2:
http://forums.netdui...dpost__p__10332

And I understand that I have to adjust the blockrange for the code.

What I am stuck on is where do I find the size of the ER_FLASH file since it does not get created when the build fails.

In CW2's post he says "but our firmware is 0x50ADC bytes" but I don't know where that figure came from.
How do I find the size of the firmware so that I can know how big to make the BlockRange?


#17750 SPI bug report (NETMF bug)

Posted by Mike P on 08 September 2011 - 11:40 AM

Hi I think this is a bug in the netMF code. Would any of you code gurus like to have look and tell me if you agree?
Feel free to visit codeplex and vote.
http://netmf.codeple...m/workitem/1219

AT91_SPI_Driver::Xaction_Stop() has CS release sequence reversed

After the SPI transaction completes the Chip Select should be released before setting MOSI, MISO and SCLK to their idle levels.
in 4.1 and 4.2RC2 the MOSI and SCLK pins are both set low before CS is deactivated.
I am not sure but perhaps SCLK should be set low or high to honour the Clock_IdleState setting.
The file is C:\MicroFrameworkPK_v4_2\DeviceCode\Targets\Native\AT91\DeviceCode\AT91_SPI\AT91__SPI.cpp
Lines 376-384 should be moved up to line 342
This would only cause a problem for slaves where the Clock_IdleState was true. In this instance an unwanted clock edge is sent before chip select is released. Depending on how the slave has been implemented this may have no effect.

Here is a capture of the SPI transfer and you can see MOSI and SCLK being set low before CS is released.traces are SCLK, MOSI, MISO, CS.
Attached File  single sample.png   4.94KB   19 downloads


#17567 What is this called?

Posted by Mike P on 05 September 2011 - 09:17 AM

Attached File  2011-09-05_2058.jpg   27.79KB   16 downloads This would be my guess.(see labels on photo) The GND plane is pretty obvious - large filled area. There is a cap between GND and what I would assume is VCC VCC is also supplied to one pin of the sensor via a resistor. This would be a current limiting resistor for the LED side of the light gate. The detctor side appears to have a connection to VCC and GND and two ouptuts. These are normally called A and B and are 90° out of phase. This allows you to work out which direction the sensor is moving. If you think of the output as a 2-bit binaty value then the signal would 0-1-3-2 going in one direction and 2-3-1-0 in the other direction.


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