Daman

I have just started playing with the netduino and a FPGA prototyping board. My first project was a very simple program to read a thermistor and display the result on 2 7-segment LEDs. I used the FPGA to drive the LEDs. Excited to get something up and running quickly I wrote a quick and dirty class that reads an analog input, converts to resistance, and then does a brut force search for the resistance in a table to convert the resistance to temperature. (had to loop about 200 times to find the correct resistance at room temperature. To smooth out the signal it created a 1k sliding average window. So I ran the program and though it was locked up because it was taking so long to get the first reading. Turned out it was taking 20 seconds to initialize the 1k array with the first 1k samples. Well since I had the FPGA and a logic analyzer I started to take some timings and here is what I discovered. I create a piece of code that simply toggled one of the digital outputs. myoutputport.Write(true); myoutputport.Write(false); I measure rising edge to falling edge time of ~95 uS. The following code snippet takes ~23 uS to run: i = (i + 1) % count; f = (byte)((sum / count)/10); i, f, sum, and count are all ints. Based on the fact that the netduino has a 48MHz clock, the above code takes just over 2000 instructions to execute, this can not be correct. I must be doing something wrong. I am fairly confident the timings are correct. I put the above code into a large loop so I could do some wall clock timings and the results confirmed what I was measuring with my 160 nS clock in the FPGA. I have tried creating release code but get the same results. Can that be? Is this CLR overhead? Do I have something misconfigured? Any help understanding would be appreciated. Thanks