4 replies to this topic

[Marco Zora]

I to all, i would like to implement a wishbone bus interface between my netduino plus and an FPGA. I know the poor performances of GPIO due to microframework structure. It is possible to implement only a low level function and integrate it in the CLR? without the need to recomplile all? thanks to all, Marco

[Spork]

i would like to implement a wishbone bus interface between my netduino plus and an FPGA.

I can't speak to your CLR question, but isn't Wishbone intended to be used between components on the FPGA? When it comes to bridging the gap between the FPGA and the Netduino, wouldn't you use i2c or SPI? There is a Wishbone compliant implementation of i2c (and probably an SPI one too) at www.OpenCores.org.

Sorry if this reply isn't a direct response to your question, but I'm wondering if you could comment.

[Marco Zora]

Wishbone is only an open bus standard. You are right, there are I2C and SPI to wishbone interfaces. BUT I2C and SPI are "relatively" slow serial bus as Wishbone is a parallel bus, so maybe it can be fast. If it were possible to drive netduino GPIO in a low level functions, you cold create a fast bridge between FPGA and netduino.

[CW2]

BUT I2C and SPI are "relatively" slow serial bus as Wishbone is a parallel bus, so maybe it can be fast.

There are two things worth considering: 1) according to the datasheet the maximum GPIO frequency is 25 MHz (resp. 30 MHz) for 40pF (resp. 20 pF) load and 2) there are only 4 consecutive bits of a port broken out on the Netduino (PB19 - PB22, the other four PB27 - PB30 have max frequency 12.5 MHz). You'd need to recompile the whole firmware to add Wishbone support.

[Marco Zora]

yes, you're right, I also believe that it is necessary to recompile everything.