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SPI Bug? Configuring Clock_IdleState==false Has No Effect


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#1 magoldsm

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Posted 13 March 2013 - 04:56 AM

Is this a bug or is it me?
 
            spiConfig = new SPI.Configuration(
                pinCS,
                false,             // SS-pin active state
                10,                 // The setup time for the SS port
                10,                 // The hold time for the SS port
                false,              // The idle state of the clock
                true,             // The sampling clock edge
                Freq,              // The SPI clock rate in KHz
                SPI_Devices.SPI1   // The used SPI bus (refers to a MOSI MISO and SCLK pinset)
            );
 
            spiBus = new SPI(spiConfig);
            spiBus.Write(new byte[] { CMD_WR | MDR0, 0x01 });   // x1 Quadrature, free-running, disable Index
 
Regardless of whether I set the idle state to TRUE or FALSE, the clock (pin 13) idles HIGH.  I verified this with a logic analyzer.  I am trying to interface to an LS7366R (http://www.lsicsi.co...ets/LS7366R.pdf) that wants the clock to idle LOW.
 
On a related note: if I have other devices that want the clock to idle HIGH, can I mix these?  Does the clock get set to the appropriate idle value before the associate CS is asserted?
 
Thanks in advance,
Michael


#2 Chris Walker

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Posted 13 March 2013 - 05:04 AM

Hi Michael, Which Netduino are you using? What version of firmware? There was a bug with the IdleClock setting in really early versions of the Netduino Plus 2 firmware. And yes...the SPI configuration should be put into effect right before the CS pin is asserted. So if your idle state is set to true, the clock line should be set high before CS is asserted and before any clocking commences. Chris

#3 magoldsm

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Posted 13 March 2013 - 05:10 AM

Netduino Plus 2:

 

 

SolutionReleaseInfo.solutionVersion:    4.2.2.2
SolutionReleaseInfo.solutionVendorInfo: Netduino Plus 2 (v4.2.2.2) by Secret Labs LLC
 
 
Thanks,
Michael


#4 Chris Walker

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Posted 13 March 2013 - 05:17 AM

Hi Michael, Can you create a small (<20 line) repro for this, and a logic analyzer screen capture? And if you're using Saleae Logic, the exported data from the logic analyzer? We'll pull it in here and repro it to see what's going on. Chris

#5 magoldsm

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Posted 13 March 2013 - 05:41 AM

I've attached two Saleae Logic files: TRUE and FALSE corresponding to the value of Clock_IdleState in the constructor.  To ensure that I was really running a different image each time, I changed the values written - that's why the runs aren't identical in the two traces..  
 
Thanks for the quick response!
 
Michael

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#6 magoldsm

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Posted 13 March 2013 - 05:46 AM

Oops.  Forgot the screen shots.

 

 

Michael

 

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#7 ajoakim

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Posted 14 March 2013 - 09:18 PM

It seems like that SPI is broken, I have issues with it my self.



#8 magoldsm

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Posted 17 March 2013 - 01:39 AM

I am successfully using the SPI interface with two chips: the ADXL345 accelerometer and the L3G4200D gyro.  These two parts differ from the LS7366R quadrature counter in that they are active HIGH clock while the LS7366R is active LOW.  Chris is looking into the problem with the LS7366R.

 

I've attached the code I'm using for the accelerometer and gyro in case you are interested.

 

 

Michael

 

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#9 magoldsm

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Posted 23 March 2013 - 05:53 AM

Were the uploads received by Secret Labs?  I haven't heard anything.  While I don't necessarily expect an analysis of the uploads, it would be nice to know if they were received and someone is either looking at them or has them on a schedule to take a look.

 

Thanks,

Michael

 



#10 Chris Walker

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Posted 30 March 2013 - 06:06 PM

Hi Michael, We have filed a bug report on this and will look into it for you. I'm wondering if there is some link between the setup/hold time and the clock state. We previously verified all four SPI clock/edge configuration options...so I'm really surprised to see this. If you invert the other settings in your code, does the clock idle get flipped the right way around? What happens if you set your setup and hold time to 0ms? We'll find this out in testing...I'm just curious in case there's a quick workaround in the meantime. Thank you very much for the repro and LOGIC screen capture, Chris

#11 Chris Walker

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Posted 30 March 2013 - 06:06 PM

It seems like that SPI is broken, I have issues with it my self.

Are you experiencing the same clock idle issue--or something else? Chris

#12 magoldsm

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Posted 01 April 2013 - 11:52 PM

Hi Michael, We have filed a bug report on this and will look into it for you. I'm wondering if there is some link between the setup/hold time and the clock state. We previously verified all four SPI clock/edge configuration options...so I'm really surprised to see this. If you invert the other settings in your code, does the clock idle get flipped the right way around? What happens if you set your setup and hold time to 0ms? We'll find this out in testing...I'm just curious in case there's a quick workaround in the meantime. Thank you very much for the repro and LOGIC screen capture, Chris

 

Hi Chris,

 

I've found the problem - very strange.  The chip I was trying to talk to was bad.  There was a partial short from Vdd to ground.  I was powering the chip from the Netduino's 3.3v supply and the short was dragging the 3.3v down to 2.48v.  What is odd is that the Netduino seemed to work just fine except for this SPI configuration problem.

 

I replaced the chip and now the 3.3v rail is at 3.3v.  And the clock idle state is correctly following the configuration.  I've got to say, this is the damnedest problem I've seen it quite a while.  I suppose *something* has to be first to fail when the supply voltage goes below margins.  I assume that the SPI protocol is generated in h/w and that the SPI.Configuration serves to initialize the protocol engine.

 

The chip is still not talking back to me correctly, but that's probably software since I haven't spend any time debugging the actual writes and reads for correct content.

 

Thanks for taking the bug report and my apologies if you or your staff spent to much time on it.

 

Michael






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